1. Field of the Invention
The present invention relates generally to a semiconductor device, in particularly to the semiconductor device having a redundant circuit implemented following testing of the device. The present invention also relates a manufacturing method therefor.
2. Description of the Background Art
Generally, in manufacturing a semiconductor device, an integrated circuit is formed on a substrate such as a wafer through a number of processes, the circuit is tested and is packed in a package. A conventional method of manufacturing a semiconductor device including a step of testing circuits will be described in the following with reference to a DRAM (Dynamic Random Access Memory).
First, a structure of the DRAM, especially of a memory cell array will be described. FIG. 3 is a schematic diagram showing a structure of a memory cell array of a conventional DRAM. Referring to FIG. 3, a plurality of word lines WL extending in a row direction and a plurality of bit lines BL extending in a column direction are arranged intersecting with each other in a memory cell array 1. A memory cell MC is provided at each of the intersections of the words lines WL and the bit lines BL. A plurality of row decoders 2 are provided corresponding to the plurality of word lines WL. Each row decoder 2 is connected to a corresponding word line WL through a word driver 3. A plurality of column decoders 4 are provided corresponding to the plurality of bit lines BL.
A spare word line SWL is provided outside of the plurality of word lines WL. A spare memory cell SMC is provided at each of the intersections between the spare word line SWL and the bit lines BL. A spare decoder 5 is provided corresponding to the spare word line SWL. The spare decoder 5 is connected to the spare word line SWL through a spare word driver 6. The spare word line SWL, the spare decoder 5 and the spare word driver 6 constitute a so-called redundant circuit.
The function of the redundant circuit will be described in the following. The redundant circuit is incorporated in a semiconductor device in order to improve production yield of the semiconductor devices. Referring to FIG. 4, description will be given of a characteristic evaluating test of a memory circuit of a DRAM and a method of repairing a defective circuit by using the redundant circuit. First, operating test of the DRAM is carried out by using a tester or the like to detect a defective bit MC1, if any, in the memory cell 1. A fuse FU1 of the word line WL1 including the defective bit MC1 is cut, thereby the defective word line WL1 is separated from the circuit. Thereafter, by cutting the fuse SFU in accordance with a prescribed combination, the circuit is adapted such that the spare line SWL operates only when a signal for selecting the defective bit MC1 is inputted as an external address signal. By connecting a spare line included in the redundant circuit to an original line, a DRAM having a defect can be repaired.
The structure of the DRAM comprising the above described redundant circuit will be described in the following. FIG. 5 schematically shows a cross sectional structure of a memory cell array of the DRAM including the redundant circuit. The memory cell 10 of the DRAM comprises a MOS transistor 11 and a capacitor 12. The MOS transistor 11 comprises source.multidot.drain regions 14, 14 formed in a silicon substrate 13 and a gate electrode 16 with a thin gate oxide film 15 interposed therebetween. The capacitor 12 comprises an insulating film 17 formed on the surface of the silicon substrate 13 and an upper electrode 18 deposited on the insulating film 17. The MOS transistor 11 and the capacitor 12 are formed in a region surrounded by a thick field oxide film 34 formed on the surface of the silicon substrate 13. The surface of the MOS transistor 11 or the capacitor 12 is covered with a first interlayer insulating film 19. An internal wiring layer 20 is connected to one side of the source.multidot.drain region 14 of the MOS transistor 11 through a contact hole formed in the first interlayer insulating film 19. A fuse portion 21 formed of polysilicon or the like included in the redundant circuit is formed above the field oxide film 34. The shape of the fuse is schematically shown in this figure. A second interlayer insulating film 22 is formed on the surface of the first interlayer insulating film 19. A wiring layer 23 formed of aluminum or the like is formed on the surface of the second interlayer insulating film 22. An end portion of the wiring layer 23 is connected to a bonding pad portion 26 formed of aluminum or the like on a flat peripheral surface of the chip. Essential circuit structure of a semiconductor device is provided by this step of forming the wiring layer 23. Thereafter, a passivation film 24 is formed to cover the entire surface on the surfaces of the wiring layer 23 and the like in order to protect the integrated circuit. A polyimide film 25 formed of a polyimide resin is formed thereon. The polyimide film is employed as an upper most protecting film since it has superior .alpha. ray resistance and superior heat resistance.
Main steps of manufacturing a conventional DRAM will be described with reference to FIGS. 6A to 6E. A cross sectional structures shown in FIGS. 6A to 6E schematically show the cross sectional structure of the DRAM shown in FIG. 5 for convenience.
FIG. 6A shows a state in which the wiring layer 23 and the bonding pad portion 26 are formed on the surface of the second interlayer insulating film 22. In this step, the surface of the bonding pad portion 26 is exposed. The circuit is tested in this state. During the circuit test, an electrode terminal 27 of a tester is pressed on the surface of the bonding pad portion 26 to detect defects of the circuit. If a defective portion of the circuit is detected, a fuse 21 provided in the redundant circuit is melted and cut by irradiating a laser beam 28 or a by applying a large current in accordance with one logic. By doing so, a defective circuit can be replaced by a good one. Now, the bonding pad portion 26 is formed of aluminum, which is very soft compared with the electrode terminal 27 which is formed of tungsten (W) or the like. Consequently, it is easily shaved when the electrode terminal 27 is strongly pressed thereon, and shavings 29 of aluminum may be scattered on the upper surface of, for example, the wiring layer 23. Such metal shavings 29 may possibly cause short circuits between the wiring layers 23 in operation. Consequently, the number of defective DRAMs is increased and the production yield of the device is lowered.
Thereafter, as shown in FIG. 6B, a passivation film 24 is formed on the surface on which the wiring layer 23 and the like are formed. Thereafter, a portion on the surface of the bonding pad portion 26 is opened by photolithography and etching using a resist pattern 30a formed on the surface of the passivation film 24 as a mask (FIG. 6C).
As shown in FIG. 6D, the polyimide film 25 is formed on the surface of the bonding pad portion 26 and on the surface of the passivation film 24.
Thereafter, as shown in FIG. 6E, a resist 30b is applied, and the polyimide film 25 on the surface of the bonding pad portion 26 is removed by photolithography and etching. Generally, the polyimide film 25 is dissolved and removed by an alkali solution. However, the alkali solution also dissolves the surface of the bonding pad portion 26 formed of aluminum. Therefore, the surface of the bonding pad 26 becomes rough after the step of patterning the polyimide film 25. The rough surface of the bonding pad 26 causes defective connection of wires for the wire bonding when it is packed in a package.
As described above, the conventional manufacturing method exhibits the following draw backs, namely,
(a) metal shavings of the bonding pad portion 26 caused by the contact during the circuit test caused short circuits between wiring layers; and
(b) the surface of the bonding pad portion 26 is made rough by the alkali solution in the step of patterning the polyimide film 25 formed directly above the surface of the bonding pad portion 26.
With regard to the above described point (a), the surfaces of the metal shavings scattered between the interconnection layers are naturally oxidized in the stage of testing the wafer, so that they are not the cause of the defects. However, at the consumer test or a final test after a burn-in test during which a high voltage is applied at a high temperature, the surfaces of the metal shavings are activated, causing defects such as short circuits. Therefore, the generation of metal shavings was a serial problem.